Parallel Processing on VLSI Arrays.pdf

Parallel Processing on VLSI Arrays

Guest Editor: JOSEF A. NOSSEK This is a special issue of the Journal of VLSI Signal Processing comprising eight contributions invited for publica­ tion on the basis of novel work presented in a special session on Parallel Processing on VLSI Arrays at the International Symposium on Circuits and Systems (ISCAS) held in New Orleans in May 1990. Massive parallelism to cope with high-speed requirements stemming from real-time applications and the restrictions in architectural and circuit design, such as regularity and local connectedness, brought about by the VLSI technology are the key questions addressed in these eight papers. They can be grouped into three subsections elaborating on: . Simulation of continuous physical systems, i. e. , numerically solving partial differential equations. . Neural architectures for image processing and pattern recognition. . Systolic architectures for implementing regular and irregular algorithms in VLSI technology. The paper by A. Fettweis and O. Nitsche advocates a signal processing approach for the numerical integration of partial differential equations (PD Es). It is based on the principles of multidimensional wave digital filters (MDWDFs) thereby preserving the passivity of energy dissipating physical systems. It is particularly suited for systems ofPDEs involving time and finite propagation speed. The basic ideas are explained using Maxwells equa­ tions as a vehicle for the derivation of a multidimensional equivalent circuit representing the spatially infinitely extended arrangement with only very few circuit elements.

Design of a Parallel Processing Unit with Systolic … [[abstract]]The design of a massively parallel processing system IPU (Integrated Parallel Processing Unit) is described in this paper. It is a two-dimensional mesh-connected parallel proccesing array operated in an SIMD fashion. The current version of the IPU array is implemented with 64 systolic VLSI chips, each of which consists of 4

5.11 MB DATEIGRÖSSE
1461368057 ISBN
Englisch SPRACHE
Parallel Processing on VLSI Arrays.pdf

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[[abstract]]The design of a massively parallel processing system IPU (Integrated Parallel Processing Unit) is described in this paper. It is a two-dimensional mesh-connected parallel proccesing array operated in an SIMD fashion. The current version of the IPU array is implemented with 64 systolic VLSI chips, each of which consists of 4

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